1. Field of the Invention
The present invention relates to a parallel processing computer, and more particular to a parallel processing computer for executing a plurality of threads concurrently and in parallel.
2. Related Art Statements
In conventional on-chip multi-threaded processors, such processors are based on serial processing in a von Neumann type. In such a circumstance even if the processor is multiprocessor having a plurality of processors, in order to asynchronously execute a plurality of internal processes, a plurality of external interruptions or events, in which number of interruptions or events is greater than number of processor resources, changing the execution environment of each processor by interrupting (i.e., preempting the control from a current running program) execution of the running program at the moment occurs frequently. This execution environment typically corresponds to control blocks such as the process control blocks (PCBs) which were generated for every process. Such control blocks are stored in the memory and are loaded in an extremely high-speed memory such as a register in the execution time. The control blocks include a lot of information such as values of respective registers, which should be used in each process, addresses at which instructions should be restarted, memory administrative information and input/output related information. It is therefore difficult to keep at a high operating rate of the processor, because the above-mentioned control mechanism becomes complicated and has larger overheads. In addition, the configuration of the program, which defines asynchronous parallel processing, becomes complicated, and in general it is difficult to program software codes for effectively achieving parallel processing.
There have been developed various multi-thread execution methods to make execution of a plurality of threads concurrently. Among them, a multiprocessor with a plurality of threads intermingling execution (which is called Simultaneous Multithreading; SMT) method to make execution concurrently by intermingling a plurality of threads in the instruction level is proposed. The SMT method has an advantage of lower development cost because it can utilize a conventional superscalar processor construction technique. However, because the code of the thread in SMT is a conventional general code and the thread is not a “nonstop (non-interruptive) exclusive execution” type thread provided by the present invention and there is no mechanism to avoid execution interruption in the thread, the execution interruption occurs generally. If as a latency, i.e., a waiting time occurs in any I/O process or any memory access during execution of the thread and thus an execution of an instruction, which follows the preceding instruction in wait sate, is delayed, the execution of the thread is interrupted in general. As for the thread which was interrupted in the execution, the execution is restarted (i.e., resumed) when a processor resource(s) becomes free. When such execution stopping or interruption arises, it is required to evacuate the execution state of the interrupted thread, and is required for the processing to recover the execution condition of the thread, which should be resumed in the execution. In principle, a problem regarding an execution environment change among threads is still remained in this prior technique in the same manner as the above-mentioned Neumann style computer.
Since the execution stopping or interruption is performed toward a thread which made a processor in an idle state due to memory access or communication with outside etc., such thread cannot expect when the execution of the thread is interrupted, that is, the thread being interrupted is blindsided by the interruption. Therefore, it is not possible to expect about the thread switch. It is a work of a scheduler (i.e., a dispatcher), which allocates a ready-to-run thread to a processor of the idle state and the detection of the idle state depends on a hardware mechanism.
Furthermore, various interruption-handling technologies for increasing in efficiency of the interruption processing in a conventional computer have been disclosed. For example, an interruption handling technology by Amamiya et al. who is the inventor of the present invention has been disclosed (refer to a Japanese patent document: Patent application laid open No. 2002-342093 (paragraphs 0006-0008, FIG. 1). This prior art is a technique, which preserves interruptions until reaching predetermined interruption number and when reaching the number the reserved interruptions are processed entirely. Although such interruption handling technique has an advantage in which existing program codes as they are can be operated due to its structure, this prior technique has some disadvantages such that an interruption processing with high-priority is forced to wait to some degree, and a hardware structure becomes complicated.
There are following problems regarding thread switch because as mentioned above conventional computers are not able to avoid change or switch processor environments when an execution interruption occurs, and thus it is difficult to keep the operating rate or performance of the processor high.    (i) Because it is not possible to expect when the execution interception occurs, that is, program code itself cannot estimates when the control of the processor is preempted, all information regarding current executing environment must be sheltered or evacuated and thus the evacuation and recovery must treat extra data.    (ii) Because an arithmetic (execution) unit is fixed or immobilized to a register, the register, which is used by the thread in execution cannot be utilized by other threads until the execution interruption or stopping occurs. In other words, it is impossible to change the execution environment in advance because it is not possible to expect.